I have succeeded in changing Anyka CPU clock ratio. As you know from the specification the CPU clock can be either equal to ASIC clock(RAM?) or PLL1 clock and can be set by registers.
From specification:
PLL1 clock is equal to:
Pll1 = 4 x M / N
M = (62, 63, 64, ..., 94;)
N = (1, 2, 3, ..., 16)
Where M = 62, N = 1 then it is 248Mhz
So theoretically the max frequency can be 94*4=376Mhz and actually changing the clock larger than 248Mhz would not be overclocking as CPU is capable of it.
Changing the clock temporary(until reboot)
For changing the clock I used the 880xDownLoadTool from BSP and the akubhost.exe command line program. The tool works similar to flasher while DL_JUMPER is shorted and allows to access the RAM directly, upload/download the code and execute it. The folder contains tools and some examples too.
Example of changing the CPU clock to 266Mhz (RAM 133Mhz):
1. Attach USB cable while DL_JUMPER is shorted
2. Create init file ddr_7802_133-266.txt with text
As you see the PLL clock is set by registers at address 0x08000004 and 0x080000dc. 0x080000dc sets the PLL1_CLK divider N=1 by default. At 0x08000004 the hex value 0xd004 sets the other register bits. 0xd004 in binary is 1101000000000100, first 4 bits sets if CPU_CLK is equal to PLL1 or ASIC clock, then 3 bits for setting ASIC_AP_EN(Audio processor?) and PLL_EN, then 3 bits for ASIC CLK divider n=1 by default if not set, and last 5 bits set the PLL1_CLK divider M=62 by default. The specification is not entirely correct about divider M as actually it is not set directly but as the sum of default value 62 plus new value.
3. Copy eboot.nb0 at the same folder as AKUBHOST tool.
4. Create batch file containing
What this does is it initializes the RAM and registers, then transfer eboot(bios) to RAM and executes it from there so effectively bypassing booting bios from flash. Of course after reboot all will be back to normal.
Changing the clock permamently
The boot process seems as follows:
1. Reset. The onchip ROM bootcore checks if to boot from USB or NAND flash.
2. If booting from NAND then the first block of NAND flash is read and copied to onchip RAM(12KB) and executed. On our netbooks this file is called nboot64_ddr_V5.0.bin (size 6KB) for 1.9 ROM.
3. NANDboot code initializes RAM, sets the registers and then copies eboot.nb0(BIOS) from flash to RAM and boots. The producer eboot seems not needed at all, guess it is used at factory.
4. Eboot (BIOS) allows to enter setup(F1) or boots the NK(Native Kernel) image - XIP.nbo from flash
5. Windows CE starts
So for permament fix the nboot needs to be hexedited and reflashed if "overclocking" seems working stable.
Some side notes:
1. If increasing the CPU_CLK audio doesn't seem to work right. Do not know the reason for now as "programmer's guide" is not available and it is not clear what causes this. Other devices seem to work OK.
2. It is impossible to set 266Mhz precisely so maybe 266Mhz netbooks are fake it would be interesting to compare the nboot files and if they match then the CPU clocks are identical. Need a dump.
Attachments:
880xDownLoadTool_files.zip My example files and needed DLL files for AK8801_MI_84M_CL2_03.exe windows download tool.
From specification:
PLL1 clock is equal to:
Pll1 = 4 x M / N
M = (62, 63, 64, ..., 94;)
N = (1, 2, 3, ..., 16)
Where M = 62, N = 1 then it is 248Mhz
So theoretically the max frequency can be 94*4=376Mhz and actually changing the clock larger than 248Mhz would not be overclocking as CPU is capable of it.
Changing the clock temporary(until reboot)
For changing the clock I used the 880xDownLoadTool from BSP and the akubhost.exe command line program. The tool works similar to flasher while DL_JUMPER is shorted and allows to access the RAM directly, upload/download the code and execute it. The folder contains tools and some examples too.
Example of changing the CPU clock to 266Mhz (RAM 133Mhz):
1. Attach USB cable while DL_JUMPER is shorted
2. Create init file ddr_7802_133-266.txt with text
- Code:
UINT reg_addr[] = {
0x080000dc, // set n
0x08000004, // set m and pll_en
0x66668888, 0x66668888,
0x20026000, 0x66668888, 0x66668888, // set uart baudrate
0x08000064, 0x080000a8, 0x2002d004, 0x66668888,
0x2002d000, 0x2002d000, 0x66668888, 0x2002d000,
0x66668888, 0x2002d000, 0x66668888, 0x2002d000,
0x66668888, 0x2002d000, 0x66668888, 0x2002d000,
0x66668888, 0x2002d000, 0x66668888, 0x2002d000,
0x2002d008};
UINT reg_value[] = {
0x0000000c, // N = D[15:12]+1
0x0000d004, // D[15:12] d:(1101 cpu=pll1, 00 asic_ap_en, 0 pll_en) 1101 000
// D[8:6] asic div(n)=pll1/(2^this) 001
// D[5:0] M=62+this 11:62M 27:84M 010001
0x000000c8, 0x000000c8,
0x30200433, 0x000000c8, 0x000000c8, // set uart baudrate 115200
0x08000000, 0x44000000, 0x0f706b95, 0x000000c8,
0x40170000, 0x40120400, 0x000000c8, 0x40104000,
0x000000c8, 0x40100123, 0x000000c8, 0x40120400,
0x000000c8, 0x40110000, 0x000000c8, 0x40110000,
0x000000c8, 0x40100023, 0x000000c8, 0x60170000,
0x01027c58};
As you see the PLL clock is set by registers at address 0x08000004 and 0x080000dc. 0x080000dc sets the PLL1_CLK divider N=1 by default. At 0x08000004 the hex value 0xd004 sets the other register bits. 0xd004 in binary is 1101000000000100, first 4 bits sets if CPU_CLK is equal to PLL1 or ASIC clock, then 3 bits for setting ASIC_AP_EN(Audio processor?) and PLL_EN, then 3 bits for ASIC CLK divider n=1 by default if not set, and last 5 bits set the PLL1_CLK divider M=62 by default. The specification is not entirely correct about divider M as actually it is not set directly but as the sum of default value 62 plus new value.
3. Copy eboot.nb0 at the same folder as AKUBHOST tool.
4. Create batch file containing
- Code:
AKUBHOST.exe /init:ddr_7802_133-266.txt /down:eboot.nb0 /down_addr:0x30038000 /go
What this does is it initializes the RAM and registers, then transfer eboot(bios) to RAM and executes it from there so effectively bypassing booting bios from flash. Of course after reboot all will be back to normal.
Changing the clock permamently
The boot process seems as follows:
1. Reset. The onchip ROM bootcore checks if to boot from USB or NAND flash.
2. If booting from NAND then the first block of NAND flash is read and copied to onchip RAM(12KB) and executed. On our netbooks this file is called nboot64_ddr_V5.0.bin (size 6KB) for 1.9 ROM.
3. NANDboot code initializes RAM, sets the registers and then copies eboot.nb0(BIOS) from flash to RAM and boots. The producer eboot seems not needed at all, guess it is used at factory.
4. Eboot (BIOS) allows to enter setup(F1) or boots the NK(Native Kernel) image - XIP.nbo from flash
5. Windows CE starts
So for permament fix the nboot needs to be hexedited and reflashed if "overclocking" seems working stable.
Some side notes:
1. If increasing the CPU_CLK audio doesn't seem to work right. Do not know the reason for now as "programmer's guide" is not available and it is not clear what causes this. Other devices seem to work OK.
2. It is impossible to set 266Mhz precisely so maybe 266Mhz netbooks are fake it would be interesting to compare the nboot files and if they match then the CPU clocks are identical. Need a dump.
Attachments:
880xDownLoadTool_files.zip My example files and needed DLL files for AK8801_MI_84M_CL2_03.exe windows download tool.
Last edited by otoluk on Tue 2 Nov 2010 - 23:15; edited 1 time in total
